A finned field effect transistor (finFET) is a FET that includes a fin-shaped channel region. A gate structure intersects the channel region, and the ends of the fin structure receive source and drain doping. The dimensions of the fin affect the operation of a finFET. For example, the length of the fin under the gate, measured in the direction from source to drain, determines the effective channel length of the device. It is desirable to form fins having a consistent height, and forming a finFET on a silicon-on-insulator (SOI) wafer provides improved fin height uniformity. This improved uniformity may be important as fin height scales.
For various applications, including system on chip (SOC) operation, it is useful to make finFETs with fins having at least two different heights. When bulk silicon is used, fin height can be controlled by removing different amounts of the shallow trench isolation (STI) oxide layer around different groups of fins. Essentially, all fins have the same height when measured from the underlying silicon layer, but different amounts of the STI oxide region are left around different fins so that different heights of the fins are left projecting from the STI layer. However, when an SOI wafer is used, the thickness of the silicon layer is predetermined, and the conventional method cannot be used without modification to achieve different fin heights. Instead, it may be necessary to form an STI layer on the SOI active silicon layer, mask the area over a fin that is to be a shorter fin and selectively etch the STI layer around another fin to form a taller fin, which is similar to the method used in bulk substrate and that undermines the intended benefit of finFET on SOI substrate.
Another known method for forming a finFET on an SOI wafer with fins having different heights is illustrated in FIGS. 1-6. FIG. 1 illustrates a conventional SOI wafer 100 that includes a substrate 102, a bottom oxide (BOX) layer 104 and an active silicon layer 106 having a top surface 108. In FIG. 2, a hardmask 202, which may comprise silicon nitride, for example, is formed on the top surface 108, and a patterned resist 204 is formed on the hardmask so that a first portion 206 of the SOI wafer 100 is masked and a second portion 208 of the SOI wafer 100 is not masked. In FIG. 3, the portion of the hardmask 202 that is not protected by the resist 204 is etched down to the top surface 108. With the top surface 108 exposed and the first portion 206 of the SOI wafer 100 protected, the top surface 108 is oxidized to form a depression 402 filled with a top oxide layer 404 as illustrated in FIG. 4. The oxidation process produces a generally symmetric oxide layer 404 which projects upwardly beyond the top surface 108 of the active silicon layer 106 about as far as it projects downwardly into the active silicon layer 106.
FIG. 5 shows the SOI wafer 100 after the hardmask 202 and patterned resist 204 have been removed at which time a first plurality of masks 502 are formed in the first portion 206 of the SOI wafer 100 and a second plurality of masks 504 are formed in the second portion 208 of the SOI wafer 100 on the top oxide layer 404. The silicon not protected by the first plurality of masks 502 in the first portion 206 and the silicon and oxide not protected by the second plurality of masks 504 in the second portion 208 are etched away to produce a plurality of fins. FIG. 6 illustrates a first plurality of fins 602 in the first portion 206 of the SOI wafer 100 that are taller than a second plurality of fins 604 in the second portion 208 of the SOI wafer 100. While this method may produce fins for a finFET that are acceptable for some applications, the uneven top surface created by the top oxide layer 404 protruding from the top surface 108 of the active silicon layer 106 may make it difficult to apply masks for later forming the first and second plurality of fins.
It would therefore be desirable to provide a method of forming fins on an SOI wafer that have different heights in a manner that does not require the addition of an STI layer to the SOI wafer and that provides a substantially even surface on which to form a mask for forming the different height fins.